Electrical Engineering Question:
What is the difference between the following two lines of Verilog code?
Answer:
What is the difference between the following two lines of Verilog code?
#5 a = b;
a = #5 b;
#5 a = b; Wait five time units before doing the action for "a = b;".
The value assigned to a will be the value of b 5 time units hence.
a = #5 b; The value of b is calculated and stored in an internal temp register.
After five time units, assign this stored value to a.
#5 a = b;
a = #5 b;
#5 a = b; Wait five time units before doing the action for "a = b;".
The value assigned to a will be the value of b 5 time units hence.
a = #5 b; The value of b is calculated and stored in an internal temp register.
After five time units, assign this stored value to a.
| Previous Question | Next Question |
| Given the following snipet of Verilog code draw out the waveforms for clk? | What is the difference between: c = foo ? a : b; and if (foo) c = a; else c = b; |